1. Technical Field
The present invention relates generally to memory circuits, and more particularly to a storage array with a local clock buffer having adjustable timing for determining internal timing margins of the array.
2. Description of the Related Art
Storage cell performance is a critical limitation in today's processing systems and is predicted to become even more of a critical limitation as technologies move forward. In particular, static random access memory (SRAM) cells are used in processor caches and external storage to provide fast access to data and program instructions. Static storage cells are also used within processors and other digital circuits for storing values internally, for example, in processor registers. With processor cycle frequencies reaching well above 4 Ghz, development of SRAM cells that can store and provide access to stored values within that period has become necessary. However, as the storage cell access times decrease, determining the internal timing margins of various portions of both read and write access cycles presents a challenge. If a probe is used to attempt to measure the internal timing of a read or write operation, the probe alters the timing of the cell, yielding incorrect results.
As storage cell access times decrease, the validity of circuit simulations also decreases, therefore, while simulations are valuable, measurements performed on actual storage devices in their fully-implemented condition, e.g., the entire storage array and access circuits, is a necessity. Timing margins are direct indicators of potential performance of a storage array design, as the timing margins dictate the relationship between potentially specified or required performance and production yields of components including the storage array design. Further, variation in timing margins from die-to-die and within a die reveal information about process variations and particular failure mechanisms.
Various techniques such as one-shot delay lines and ring oscillators have been used to obtain data on portions of the internal timing of storage cells. However, a complete model of timing margins based on measurements made by such circuits must generally include summing measurements from multiple test circuits that include the individual timing portion measurement capability in order to obtain the overall timing margin. Including all of the delay and/or ring oscillator test circuits required to implement a complete timing margin may consume significant circuit area and may also require modification of the layout of the device incorporating the test circuits. Further, there is generally a probing requirement associated with such measurement, requiring test pads than may not be practical in production circuits, or that would require significant disruption of the layout in order to provide the test pads. Finally, such techniques typically do not measure the performance of an individual storage cell, due to the aggregation of storage cell performance in ring oscillator and delay line circuits. It is desirable to measure the performance of each cell in an array due to variation in device characteristics across the array and due to worst-case signal timing conditions at various positions within the array.
It is therefore desirable to provide a test circuit and method for accurately determining the internal timing margins of storage cells, including individual cells, under the operating conditions of an actual storage array. It is further desirable to provide such a test circuit that requires only a small circuit area to implement, so that the test circuit may easily be incorporated in a production storage array and does not significantly perturb the array and access circuitry design.